1. Field of the Invention
The present invention relates to an AND circuit and also to an address circuit employing such AND circuits and, more particularly, to an integrated memory circuit employing the address circuit which has a short delay time and can be assembled in a small layout area using bipolar CMOS circuit forming techniques.
2. Description of the Prior Art
In FIG. 11 , an example of a prior art AND circuit is shown which is constructed using bipolar CMOS circuit technology. This is disclosed, for example, in a document entitled "Bipolar CMOS RAM for the High Speed and High Density Memory" in NIKKEI Electronic (1986, 3-10, PP 199-217).
With reference to FIG. 11 , refe characters 1101, 1102 and 1105 designate P-channel MOSFET; 1103, 1104 and 1106, N-channel MOS FET; 1107 and 1108, NPN bipolar transistor; 1109 and 1110, resistors; 1111, a first input terminal; 1112, a second input terminal; 1113, NAND output terminal; and 1114, AND output terminal.
The following description will be directed to the operation of the AND circuit mentioned above. When the first input terminal 1111 and the second input terminal 1112 are in HIGH level, P-channel MOS FETs 1101 and 1102 are in a nonconductive state so that these FETs 1101 and 1102, close to supply no electric current from a power supply line Vcc. On the other hand, since N-channel MOS FETs 1103 and 1104 are in a conductive state, the electric potential at the NAND output terminal 1113 is in LOW level through the N-channel MOS FETs 1103 and 1104. As a result, P-channel MOS FET 1105 is in a conductive state while N-channel MOS FET 1106 is in a non-conductive state. Accordingly, NPN bipolar transistor 1107 is provided with an electric current at the base thereof to allow collector-emitter current to pass therethrough. Then, the output terminal 1114 of the AND circuit is in HIGH level. On the other hand, the NPN bipolar transistor 1108 receives no electric current to the base thereof to allow no collecto-remitter current to pass therethrough. As a result, the output terminal 1114 of the AND circuit is maintained at HIGH level.
Next, when either one of the first input terminal 1111 and the second input terminal 1112 is in a LOW level, either P type channel MOS FETS 1101 or 1102 is in a conductive state and is provided with the electric current from the power supply line Vcc. At this time, since either N type channel MOS FET 1103 or 1104 is in non-conductive state, the output terminal 1113 of the NAND is in HIGH level. Then, P type channel MOS FET 1105 is in a non-conductive state whereas N type channel MOS FET 1106 is in a conductive state. Accordingly, NPN bipolar transistor 1107 has the base supplied with no electric current and NPN bipolar transistor 1108 may receive through MOS FET 1106 a discharging current from line 1114, and hence the output terminal 1114 of AND is reduced to a LOW level.
FIG. 12 is a block diagram showing an example of an address circuit employing the AND circuit shown in FIG. 11 in combination with a word line driving circuit for driving a word line in a synchronized manner with respect to clocks.
With reference to FIG. 12, reference numeral 1201 designates a clock signal driving circuit; reference numeral 1202, a clock input line; a reference numeral 1203, a clock output line; reference numeral 1204, a decoder; reference numerals 1205.sub.i (i=1. . . n), an address input line; reference numerals 1206.sub.i (i=1 . . . 2.sup.n), an address output line; a reference numeral 1207, a word line driver; reference numerals 1208.sub.i (i=1 . . . 2.sup.n), AND circuits; reference numerals 1209.sub.i (i=1. . . 2.sup.n), word lines; reference numerals 1210.sub.i (i=1 . . . 2.sup.n), NAND circuit and reference numerals 1211.sub.i (i=1 . . . 2.sup.n), invertors.
The operation of the word line driver will be described. During a LOW level period of the clock signal at the clock output line 1202 in response to the clock input line 1201, decoder 1204 produces a HIGH level signal on one of its outputs 1206 .sub.i and produces LOW level signals on the remaining 2 -1 outputs. At this time, since the clock output line 1203 is in LOW level, 2.sup.n AND circuits 1208.sub.1 . . . 1208.sub.2n are all disabled to produce a LOW level signal from all of the AND output terminals 1114.sub.1 . . . 1114.sub.2n. Accordingly, all of the 2.sup.n word lines 1209 are in LOW level to carry out no selection operation of word lines.
Next, during a HIGH level period of the clock signal at the clock output line 1203 in response to the clock input line 1202, decoder 1204 produces a HIGH level signal on said one of its outputs 1206.sub.i so that the AND circuit 1208.sub.i connected to said output 1206.sub.i is enabled to produce a HIGH level signal from its output 1114.sub.i, and the remaining AND circuits are maintained disabled. Accordingly, only the word line 1209 connected to the AND output terminal 1114 in HIGH level is in HIGH level to carry out the operation for selecting the word line.
As understood from the above description, according to the prior art word line driving circuit of a clock synchronizing type, the AND circuit usually has a logic part formed by CMOS circuit technology and an output driver formed by bipolar circuit technology.
Thus, according to the prior art, the AND circuit employed in the word line driving circuit of a clock synchronizing type is manufactured by the CMOS circuit technology for forming the logic part and the bipolar circuit technology for forming the driver at the output stage. However the prior art word line driving circuit has a disadvantage that it is necessary to use a large number of the MOS transistors and bipolar transistors for forming one AND circuit and, as a consequence, a large area for the layout of the word line driving circuit is necessary.
Further, the word line driving circuit is required to have all of 2.sup.n gates of the AND circuit supplied with signals from the clock output lines for achievement of the clock synchronization. Therefore, there is a problem to require a large size of gate capacitance, resulting in increase of the delay time at the word driving time.